1. Field of Invention
The present invention relates to integrated circuits (ICs) generally and more particularly to determining effects related to negative bias temperature instability (NBTI) for dynamic operation of an integrated circuit.
2. Description of Related Art
For ICs with PMOS structures (e.g., a p-channel MOSFET (metal-oxide-semiconductor field-effect transistor)), NBTI has been recognized as a critical limitation for technology scaling in deep sub-micron devices [1] [2] [3] [4]. In general, NBTI degrades PMOS devices by shifting threshold voltages and reducing drive currents, thus raising an important concern for analog and digital circuits.
Although the operational setting is typically dynamic or AC (Alternating Current), at least some conventional modeling relies on static or DC (Direct Current) analysis. However, recent dynamic NBTI tests have indicated that in some cases the interface states generated during the on-state of these transistors are partially annealed during the off-state. Consequently, the predictions based on the static NBTI tests, where the transistor is always on, may be too pessimistic. Therefore, it is critically important to take into account the NBTI recovery effect in NBTI reliability modeling and reliability simulation.
Thus, there is a need for improved determination of NBTI effects for dynamic operation of an IC.